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1. Field of the Invention
The present invention relates to power management systems, and more particularly, to a configurable power management system.
2. Description of the Related Art
Previous power management systems for use with integrated circuit (IC) chips have been limited in their ability to be configured. Thus, there is a need for a power management system which is configurable.
The present invention provides an oscillator interface for use in a power management system. An interface circuit interfaces with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and bypasses the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and starts back up with a rising transition of the oscillations.
The present invention also provides a power recycle circuit for use in a power management system. An input receives a clock signal. A detection circuit for senses a minimum disable pulse when a clock signal is received and when a clock signal is not received. A power recycle circuit generates a power recycle signal in response to the minimum disable pulse. A state machine holds the power recycle signal for at least two clock cycles.
The present invention also provides a pad clock and self test circuit for use in a power management system. An input receives an oscillator clock. A clock generation circuit generates at a clock output a first pad clock having a frequency approximately equal to one-half a frequency of the oscillator clock, a second pad clock having a frequency that is forced equal to a programmable fraction of the frequency of the oscillator clock, and a low signal. The clock generation circuit has a first operating mode in which the second pad clock is generated and a second mode in which internal signals of the power management system can be observed and the clock output is forced to a known level.
The present invention also provides a clock enable circuit for use in a power management system. A clock branch generator generates a first clock signal to drive a sequential device which is internal to the power management system. A clock enabling/disabling circuit disables the first clock after a falling edge on an internal source clock, holds the first clock low during disabling, re-enables the first clock after a falling edge of the internal source clock, and subsequently begins a first rise of the first clock with a next rising transition of the internal source clock. The clock enabling/disabling circuitry does not stop an external CPU core clock when the external CPU is actively performing a bus cycle.
The present invention also provides a power level detect circuit for use in a power management system. An analog voltage-level detector interface has a programmable override function for providing a digitally encoded voltage level as an output which is used for global configuration. An input receives an analog enable signal to turn on a DC-current source of an external voltage-level detector and a read strobe. A voltage-level detector input is sampled.
The present invention also provides an internal source clock generation circuit for use in a power management system. A synchronous counter with a synchronous load to a count of one and an a synchronous clear has a plurality of count output signals. A first multiplexer having two outputs is coupled to the synchronous counter and receives the plurality of count output signals. A second multiplexer having one output is coupled to the first multiplexer. A flip-flop is coupled to the output of the second multiplexer, and a clock referenced to an external oscillator clock samples an output of the flip-flop.
The present invention also provides a power-save mode change detection circuit for use in a power management system including an internal source clock, a first bank of flip-flops coupled to the internal source clock, and a second bank of flip-flops coupled to the internal source clock. A comparator compares the first and second banks of flip-flops and generates an equality signal when there is a difference between storage values of the first and second banks of flip-flops. A change indicator is asserted when a power-save mode is asserted in one of the first and second banks of flip-flops. The change indicator is sampled with a clock which is referenced to a falling edge of a system clock, and a synchronous load 1 pulse is generated until a next rising edge of an internally qualified reference an external oscillator clock.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.